1. Field of the Invention
The present invention relates to a semiconductor device, in particular, to a semiconductor device that generates a phase-adjusted output signal.
2. Description of Related Art
Synchronous memories, which operate in synchronization with a clock signal, have been widely used as memories for personal computers and so forth. DDR (Double Data Rate) type synchronous memories are provided with a DLL (Delay Locked Loop) circuit which generates an inner clock signal (for example, an input/output clock signal) that causes output data to synchronize with an external clock signal.
A DLL circuit has a counter circuit and a delay circuit. The counter circuit updates a count value on the basis of the difference between the phase of the external clock signal and the phase of the inner clock signal. The delay circuit delays the external clock signal on the basis of the count value of the counter circuit and thereby generates the inner clock signal.
As the delay circuit, a circuit that has a coarse adjustment section and a fine adjustment section is known. The coarse adjustment section delays the external clock signal at a relatively coarse pitch. The fine adjustment section delays the external clock signal at a relatively fine adjustment pitch.
For example, the coarse adjustment section has a delay line and a selection circuit. The delay line, which is composed of a plurality of delay elements that are connected in series, delays the external clock signal. The selection circuit selects two signals LCLKE and LCLKO from output signals of the plurality of delay elements on the basis of a delay control adjustment code, and outputs the two signals LCLKE and LCLKO to the fine adjustment section.
For example, the fine adjustment section adjusts the phase of input/output clock signal LCLK, which becomes an output signal, in the range from the phase of signal LCLKE to the phase of signal LCLKO on the basis of the delay amount adjustment code.
As the fine adjustment section, for example, a fine delay circuit that has a plurality of clocked inverters is known as disclosed in Patent Literature 1 that is JP2001-326563A (see FIG. 8).
The fine delay circuit that is described in FIG. 8 in Patent Literature 1 has a clocked inverter block (hereinafter referred to as “first clocked inverter circuit”) in which clocked inverters that accept one of two input signals are connected in parallel; and another clocked inverter block (hereinafter referred to as “second clocked inverter circuit”) in which clocked inverters that accept the other of the two input signals are connected in parallel.
In the fine delay circuit described in FIG. 8 in Patent Literature 1, all the clocked inverters in the second clocked inverter circuit accept addresses (delay amount adjustment control signals) that are used to set the delay amount of the fine delay circuit. All the clocked inverters in the second clocked inverter circuit are turned on or off on the basis of the addresses.
The inventors of the present invention have found out that in the fine adjustment section, under a situation in which all the clocked inverters (output ports) that accept one of two input signals are selectively turned on or off on the basis of the delay adjustment control signals, if all the clocked inverters are turned off, the phase adjustment accuracy of the fine adjustment section fluctuates. Next, this point will be described with reference to FIG. 1 to FIG. 4.
FIG. 1 is a schematic diagram showing an example of fine adjustment section 200 in which all clocked inverters are turned on or off based on adjustment code CODE (delay adjustment control signal).
In fine adjustment section 200, each of clocked inverters 201a to 201d that are connected in parallel, which compose clocked inverter circuit 201, accepts adjustment code CODE from its own control terminal. Each of clocked inverters 201a to 201d is turned on or off based on adjustment code CODE. Each of clocked inverters 201a to 201d outputs a signal based on signal LCLKE when being turned on.
On the other hand, each of clocked inverters 202a to 202d that are connected in parallel, which compose clocked inverter circuit 202, accepts adjustment code CODEB, which is generated by inverting adjustment code CODE, from its own control terminal through inverter circuit 203. Each of clocked inverters 202a to 202d is turned on or off based on adjustment code CODEB. Each of clocked inverters 202a to 202d outputs a signal based on signal LCLKO when turned on.
Synthesizing section 204 synthesizes signals that are output from clocked inverters 201a to 201d and signals that are output from clocked inverters 202a to 202d to generate input/output clock signal LCLK.
Numerals described in individual clocked inverters represent the ratios of gate widths of clocked inverters (hereinafter they may be referred to as “sizes”). In the example shown in FIG. 1, assuming that the sizes of clocked inverters 201a and 202a are 1, the sizes of clocked inverters 201b, 201c, and 201d (and clocked inverters 202b, 202c, and 202d) become 2, 4, and 8, respectively. In accordance with the size of a clocked inverter becoming larger, the drive capability of the clocked inverter becomes larger and the dynamic resistance of the clocked inverter becomes smaller.
FIG. 2 is a schematic diagram showing the relationship of signal LCLKE, signal LCLKO, adjustment code CODE, and input/output clock signal LCLK.
As shown in FIG. 2, the edge position of input/output clock signal LCLK moves between the edge position of signal LCLKE and the edge position of signal LCLKO on the basis of adjustment code CODE.
It is assumed that when all clocked inverters 201a to 201d on the signal LCLKE side are turned on (CODE=0000), synthesized size W of fine adjustment section 200 is W=15 and that when all clocked inverters 202a to 202d on the signal LCLKO side are turned on (CODE=1111), synthesized size W is W=−15. While adjustment code CODE is incremented by 1 from 0000 to 1111 and then decremented by 1, synthesized size W varies as 15, 13, 11, 9, 7, 5, 3, 1, −1, −3, −5, −7, −9, −11, −13, −15, −13, −11, . . . and so forth. In other words, if the change width of adjustment code CODE is 1, the change width of synthesized size W becomes 2 as a constant value.
However, as shown in FIG. 3, the inventors of the present invention have found out that when adjustment code CODE varies from “CODE=0000” (minimum code) to “CODE=0001” and when adjustment code CODE varies from “CODE=1111” (maximum code) to “CODE=1110,” the phase (delay amount) of input/output clock signal LCLK, which is a real output signal of fine adjustment section 200, largely fluctuates. FIG. 3 is a schematic diagram showing the relationship between the phase step of input/output clock signal LCLK and adjustment code CODE.
A study that is conducted by the inventors of the present invention has revealed that such a large fluctuation may occur because the change of the current that can flow in one clocked inverter circuit, when the synthesized size of the one clocked inverter circuit is changed by a predetermined value in a situation in which the synthesized size is close to 0, is different from the change of the current that can flow in the clocked inverter circuit when the synthesized size is changed by the predetermined value in a situation in which the synthesized size is not close to 0.
FIG. 4 is a schematic diagram showing the relationship between the synthesized size of clocked inverter circuit 202 that accepts signal LCLKO and the current that flows in clocked inverter circuit 202.
In FIG. 4, increase D0 of the current, which flows from clocked inverter circuit 202 when the synthesized size of clocked inverter circuit 202 increases from “0” to “1”, is different from increase D1 of the current that flows from clocked inverter circuit 202 when the synthesized size of clocked inverter circuit 202 increases from “1” to “2.”
Increase D1 of the current that flows from clocked inverter circuit 202 when the synthesized size of clocked inverter circuit 202 increases from “1” to “2” is equal to increase D2 of the current that flows from clocked inverter circuit 202 when the synthesized size of clocked inverter circuit 202 increases from “2” to “3.”
Thus, in the fine adjustment section, in a situation in which all clocked inverters (output ports) that accept one of two input signals are selectively turned on or off, if all the clocked inverters are turned off, it becomes difficult to accurately control the current that flows from the clocked inverters.